In response to a recent 3DCenter post about the characteristics of the Navi 3X chips, the well-known insider Greymon55 pointed out an error in the memory bus width values for the new line of AMD chips. Apparently, the flagship Navi 31 will receive a 384-bit bus (instead of 256 bits), Navi 32 – 256-bit (instead of 192 bits), and Navi 33 – 128-bit.
The latest rumors also indicate that the Navi 31 will have one GCD (Graphics Compute Die) and 6 MCDs (Memory Compute Dies), which is quite different from the previously mentioned MCM design.
We remind you that information from insiders may not coincide with reality, and therefore it is recommended to take it with a grain of salt.
