The RISC-V architecture is quite young and is usually associated with cost-effective chips on boards like the Raspberry Pi. However, technically, it also allows you to create powerful processors that can compete with the best solutions based on the Arm and x86 architectures. At the RISC-V summit, Ventana Micro Systems announced a whole family of high-performance processors, the first of which was the Veyron V1 chip, which, according to the developers, will be able to compete in single-thread performance with the latest high-end CPUs.
Veyron V1 should be the fastest processor with RISC-V architecture. Source: Twitter@risc_v
The novelty is aimed at the hyperscaler market, and thanks to the chiplet design, the new processor was originally developed as customizable for customer tasks. Veyron V1 will be offered in the form of a kind of kit-constructor, which includes one or more Veyron computing chiplets, an I / O hub and an interconnect that allows you to connect all the components together. This, according to the developers, should seriously speed up and reduce the cost of introducing a new processor platform, reducing chip development costs by 75%, and the creation time to no more than two years.
The Veyron V1 platform is versatile and covers a wide range of applications. Source here and below: StorageReview
The Veyron V1 compute chiplet uses advanced 64-bit RISC-V cores and features 2 MB L2 cache, as well as a multi-threaded memory controller. Chiplet configurations are available with 6, 8, 12, or 16 cores at around 3 GHz, which is comparable to Google and AWS solutions. The processor can be used not only in the data center, but also in various embedded systems, 5G base stations or even client workstations.
The chip architecture will speed up the development and implementation cycle, as well as simplify the task of connecting custom accelerators
The architectural design of the Veyron V1 uses an eight-stage, out-of-order, aggressive pipeline. The chip is capable of operating at up to 3.6GHz using TSMC’s 5nm process technology. The I/O hub can be made using cheaper 12nm or even 16nm processes. A special low-latency D2D interconnect was developed to connect the processor components.
Veyron V1 development platform and specifications
Each chiplet includes up to 16 cores, and the processor can be scaled up to 192 cores in 12 chiplets. The total shared L3 cache is 48 MB. A high level of protection of the architecture against attacks through third-party channels is declared. The developers claim unprecedented low power consumption: 128 V1 cores will fit into 280 W; AMD EPYC 7763 consumes the same amount with half the number of cores.
Ventana will support the new platform at all levels of system and application software development
Ventana’s announcement cannot be called “paper” – the company talks about the availability of developer kits, moreover, in two types of chassis at once: in a desktop and in a 2U server chassis. Configuration includes 16-core V1, 128GB DDR5 connected via CXL (PCIe 5.0) x16 interface, two free PCIe 5.0 x16 expansion slots, NVMe M.2 boot drive, and 8 NVMe SFF 2.5″ SSD 1GbE port for remote management.
Most of the critical software has already been ported to the RISC-V architecture
The company has not forgotten about software support either: the Ventana Veyron V1 developer platforms will be accompanied by a full-fledged SDK with the main software already ported to the new architecture. The list includes the GCC and LLVM compilers, the OpenOCD/GDB debugger, U-Boot and Tianocore UEFI EDK2.1 loader sources and binaries. A number of Linux distributions are supported, as well as other system and application software. The new systems are expected to be available early next year.
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