As part of the recent presentation of AMD’s Ryzen 9 7950X3D and 7900X3D, it became apparent that the 3D V-Cache only sits on one of the two core complex dies (CCD) or simply chiplet, which is why the second CCD without the addition -Cache can clock higher. This also explains the low boost clock rates of the smaller Ryzen 7 7800X3D with only one CCD and the stack cache on it.
As Techpowerup.com reports, AMD has since released high-resolution renders of the dual CCD processors, which also show only one of the two CCDs with the stacked L3D (L3 cache die), clarifying the matter. The same could therefore already be seen in real images of the 3D V-Cache CCDs of the older 5800X3D based on “Zen 3” or the “Milan-X” processors of the Epyc series with 3D V-Cache. Here there is a clear appearance with dividing lines between the L3D and the structural substrates over the areas of the CCD containing the CPU cores. Previously, it had been suspected that the cache could possibly be divided between both CCDs.
Allocation and OS scheduling
According to the report, the asymmetric cache setup shouldn’t cause any “problems” from a software perspective, since AMD was already using “Alder Lake” and Co., for example with the “Zen 2” processors, even before the age of hybrid core processors. based Ryzen 3000 CPUs, dual CCD client processors and worked closely with Microsoft to optimize OS scheduling. This means that powerful and less parallelized workloads such as games can only be localized on one of the two CCDs in order to minimize DDR4 memory round trips.
Already with “Zen” and “Zen 2” there have been challenges in optimizing multithreading workloads, where the OS scheduler ideally wants to localize game workloads on a single CCX before both CCXs “saturate” on a single CCD. are, and then moves on to the next CCD.
This is achieved through methods such as “CPPC2 preferred-core flagging”, which is why AMD strongly recommends using the “Ryzen Balanced” Windows power plan included in the chipset drivers. Techpowerup.com expects something similar to happen with the 12- and 16-core 7000X3D processors. Here, gaming workloads could benefit from being localized on the 3D V-Cache enabled CCD, and any spillover workloads (like audio stack, network stack, background services, etc.) are handled by the second CCD.
Meanwhile, with non-gaming workloads spread across all 16 cores, the processor performs like any other multi-core chip, except that the cores in the 3D-V-enabled CCD perform better due to the larger victim cache. Thus, there should be no runtime errors caused by ISA mismatch since the CPU core types on both CCDs are the same “Zen 4” types. What the whole thing looks like in terms of performance will be shown in tests for the market launch in February.