At ISSCC 2023, SK hynix made a presentation announcing the development of 3D NAND flash memory with over 300 layers. The document was prepared by 35 engineers of the company, which once again emphasizes the complexity of improving the technical process for the production of multilayer flash memory. It is noteworthy that the developers intend not only to increase the recording density, but also significantly increase the throughput of the chips: from 164 MB / s to 194 MB / s.
It is easy to understand that SK hynix engineers are working on two main and most important areas: they intend to increase the recording density (reduce the cost of storing each bit of data) and increase performance. With the advent of “multi-story” 3D NAND, increasing the recording density has become quite simple in idea, but difficult to execute – this is an increase in the number of layers while reducing the step between layers. Both lead to an increase in the resistance of the wordline (WL) line connecting the cells in the matrix row. This growth has to be compensated in one way or another, otherwise speed and energy efficiency will suffer.
SK hynix talked about a hypothetical NAND memory chip with more than 300 layers, which consists of three-bit (TLC) cells and boasts a capacity of 1 Tbit. By increasing the number of layers, the cell density will increase from 11.55 Gb / mm2 for the current 238-layer memory to more than 20 Gb / mm2. It is proposed to raise the overall memory performance in five separate ways, generally aimed at speeding up the processes of writing, erasing and reading. To do this, you will have to make changes to the sequences and timings of commands.
In particular, it is proposed to implement a triple programming verification method (TPGM) instead of the previously double DPGM verification. In the new version, the cells will be divided into four groups, not three. The TPGM technology reduces the tPROG parameter and this together with the increased breakdown by about 10% will reduce cell programming time.
Also, the tPROG parameter will be reduced by the new Adaptive Unselected Line Precharge (AUSP) technology. This will speed up the work with cells by about 2%. A little more acceleration comes from reducing the capacitive load on the WL line, which will provide the programmable dummy string (PDS) method. The All Pass Rise (APR) method will result in a reduction in read time (tR), resulting in a faster response time for the WL line to a new voltage level and a 2% improvement in read time. Finally, Planar Layer Reread (PLRR) will be applied to improve the quality of service during erasure.
All together, as mentioned above, will increase the speed of 1-Tbit 3D NAND TLC from SK hynix in a generation from 164 MB / s to 194 MB / s with a simultaneous increase in recording density. To clarify, company representatives did not and could hardly disclose the production schedule for the release of NAND 300+ memory. It can be expected that the first prototypes will begin to appear by the end of the year or even not until the beginning of 2024. In the meantime, and during the current year, memory with 230+ layers will be in production, the release of which, to one degree or another, has been established by all the main players in the NAND memory market.
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