SK hynix at ISSCC 2023 presented the idea of 3D NAND flash memory with over 300 layers. Developers are looking to increase chip throughput from 164 MB/s to 194 MB/s.
SK hynix engineers intend to increase recording density and performance at the same time. In the new 3D NAND, the number of layers has increased and the step between them has decreased, which leads to an increase in the resistance of the wordline (WL) line connecting the cells in the matrix row. If this growth is not compensated, then the speed and energy efficiency will decrease.
SK hynix talked about a NAND memory chip with more than 300 layers, which consists of three-bit (TLC) cells and has a capacity of 1 Tbit. Due to the increase in the number of layers, the cell density will increase from 11.55 Gb / mm2 for 238-layer memory to more than 20 Gb / mm2.
Memory performance can theoretically be improved in five ways, aimed at speeding up the write, erase and read processes. To do this, you will have to make changes to the sequences and timings of commands, the engineers say.
So, they propose to implement a triple program verification method (TPGM) instead of the previously double DPGM verification. Then the cells will be divided into four groups, not three. The TPGM technology reduces the tPROG parameter and together with the increased split it will reduce cell programming time by about 10%.
Unselected String Adaptive Precharge (AUSP) technology will reduce the tPROG parameter. This will speed up the work with cells by about 2%.
Additional acceleration can be obtained by reducing the capacitive load on the WL line, which will provide the programmable dummy string (PDS) method. The All Pass Rise (APR) method will result in a reduction in read time (tR). This translates into a reduction in the response time of the WL line to a new voltage level and improves the read time by 2%.
To improve the quality of service during erasing, a Plane Level Reread (PLRR) technique can be applied.
As a result, according to SK hynix, the speed of 1-Tbit 3D NAND TLC will increase from 164 MB / s to 194 MB / s with a simultaneous increase in recording density.
The first 3D NAND prototypes will start appearing by the end of the year or early 2024.
