The source reports that researchers at the Japanese company Kioxia have successfully tested NAND memory with 7 bits of data written to each cell. The company talked about writing 6 bits of data to a cell in the summer of 2021. So far, these are experiments, but everything goes to the fact that recording 6, 7 and even 8 bits per cell will eventually be implemented in commercial silicon.
So far, cryogenic temperatures are required to achieve such a high data density in a cell. The memory controller needs to record and recognize 128 charge levels (threshold voltage) in one cell in order to work with the 7 bits of information recorded in it. This is twice as much as when decoding a 6-bit cell, which at one time also had to be cooled to a temperature of -196 ° C.
During the experiments, it turned out that the polycrystalline silicon used for the transistor channels is very noisy and does not allow one to unambiguously determine the set of charge states in the memory cells. The way out was found in the transition to the use of single-crystal silicon in the channels, and this had an effect – the 7-bit cell worked.
However, an unexpected difficulty arose: there were no necessary letters to designate a 7-bit cell. The abbreviation HLC (Hepta-Level Cell) was occupied by a 6-bit cell (Hexa-Level Cell), and SLC (Septi-Level Cell) was occupied by a single-bit cell.
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