AMD has revealed fresh details about the upcoming Venice generation EPYC processors, and at the same time presented information about the Zen 6 architecture. This allows us to evaluate the potential capabilities of the next generation of AMD desktop processors – the conditional Ryzen 10000, which will be built on the same architecture.
One of the key innovations of the Zen 6 architecture is an increase in chiplet component density (CCD). The Zen 6 architecture allows for 12 performance cores and 48 MB of shared L3 cache on a single chiplet. For comparison: in Zen 5, one chiplet can accommodate up to 8 cores and 32 MB of L3 cache. At the same time, the cache volume per core in Zen 6 remains the same and is 4 MB. The Zen 6 design also opens up the possibility of creating 24-core Ryzen processors using two of these CCD chiplets.
Current 12-core AMD processors use two separate chiplets. Moving all 12 cores to one CCD in Zen 6 will eliminate the inter-chip latency penalty when exchanging data in games.
AMD also claims a significant increase in IPC (instructions executed per clock). In server tests of Zen 6c dense cores, the increase in geometric average IPC in AI tasks and server loads was about 27%. AMD manufactures EPYC Venice server processors using TSMC’s 2nm N2P process in an effort to improve power efficiency and increase maximum clock speeds in certain server configurations. The company has not yet confirmed the specifications of the respective Ryzen models, however, all previous generations of Ryzen and EPYC processors were based on the same Zen architecture.
The new architecture also improves the branch prediction system: expanded queues, added a 64-entry return address stack, and processes up to two selected branches per clock cycle. The capacity of the operation cache has been increased to approximately 6750 operations, and the execution unit (front end) is capable of delivering up to 18 operations per clock cycle. In practice, this means that the processor has a better means of predicting what instructions it will need next. In cases where the prediction turns out to be incorrect, the architecture, according to AMD, is able to recover faster, which reduces the amount of wasted work.
For gaming, this can be just as important as increasing the number of cores. The vast majority of games still rely heavily on the performance of just a few threads. Improved branch prediction, faster error recovery, and efficient instruction execution can improve performance even when additional Zen 6 cores are largely idle.
The Zen 6 architecture also opens up new prospects for the Ryzen X3D line of processors. The new layout will allow AMD to release a 12-core Ryzen X3D gaming processor based on a single chip. Using the example of Venice-X server chips, the possibility of integrating a 96 MB 3D V-Cache overlay cache on top of the built-in 48 MB L3 was confirmed. In total, this gives 144 MB of L3 cache per 12-core chiplet.
Dual-chip X3D processors require complex scheduler logic to distribute game threads among the cores with the largest cache capacity. A single CCD chiplet with twelve Zen 6 cores, equipped with a huge amount of cache memory, will greatly simplify this process. This will solve the problem of thread distribution, which is typical for modern dual-chip Ryzen 9 X3D processors, and will relieve the user of the choice between the pure gaming performance of 8-core models and the multi-threading of older CPUs.
We won’t know what real boost in gaming performance the new Ryzen desktops will provide until the results of their independent tests appear. Server IPC performance is not a predictor of gaming performance, and architectural improvements will not eliminate all sources of latency.
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