The memory crisis is about to strike: Memory will eat up two-thirds of AI infrastructure capex

Global cloud providers are accelerating investments in artificial intelligence infrastructure. Total capital expenditures by the largest operators are expected to increase by 98% by the end of 2026 and by a further 50% in 2027 TrendForce.

Image source: nvidia.com

Part of this rapid growth is due to sharp increases in memory contract prices and high demand for them. In 2026, DRAM and NAND will account for 47% of cloud provider capital expenditures, growing to 68% in 2027. Starting from the second half of 2025, memory contract prices will rise significantly, causing this project to account for a significant increase in operator expenditures. Server DRAM prices will rise by a cumulative 64% in the second half of 2025, and may rise by another 270% in 2026. Enterprise SSD prices rose by about 35% in the second half of last year and may rise another 235% this year.

Image source: trendforce.com

In the second quarter of 2026, memory chip manufacturers began signing long-term agreements with customers, some of which included price caps that could curb further price increases. However, HBM’s contract prices could rise another 70-140% by 2027. By 2026, HBM and server RDIMMs combined will account for 51% of DRAM supply (in terms of bits). In 2027, the migration to new processes and the introduction of additional capacity will help increase the supply of server DRAM and HBM by another 27%. Rising memory contract prices, especially expensive HBM, combined with increased supply will result in the share of cloud provider capital expenditures reaching 68% in 2027. This will have two major impacts on the AI ​​ecosystem.

First, server hardware and AI accelerator vendors will have more reasons to raise prices on their products. As a result, cloud providers will have to further increase capital expenditures if they want to maintain planned purchases of AI accelerators. Secondly, operators can start to actively optimize the architecture of artificial intelligence systems and reduce the amount of memory in each system. In particular, RDIMM configurations and the number of HBMs integrated into future AI accelerators may change. Additionally, interest may grow in specialized AI ASICs, where the architecture of a specific model is implemented directly at the hardware level.