Micron Technology, as the world’s third largest DRAM manufacturer, participated in the Hot Chips 2026 conference and specifically discussed current issues in the development of the AI industry from the perspective of the evolution of memory production technology. Micron representatives said that artificial intelligence systems are increasingly encountering so-called “memory walls” during the development process.
Image source: Micron Technology
High bandwidth memory (HBM) architect Raghu Sreeramaneni represents Micron Technology express concern There are several factors. First of all, it is well known that the industry’s concentration on multi-layer production of vertically stacked memories such as HBM3E has significantly increased the consumption of silicon wafers, leading to the formation of a shortage of DDR5. The production of the first type of memory requires three times as much silicon.
In particular, the HBM4 architecture involves running 256 banks in parallel on a single chip, while DDR5 is limited to 32 banks. This has led to a significant increase in silicon consumption and exacerbated the memory shortage, causing prices to rise steadily. With each new generation of HBM, the gap with traditional DRAM will only grow wider. At the same time, the cost of HBM is already five times that of DDR5 on a per-foot basis, which prompts manufacturers to sacrifice the needs of the latter’s customers in pursuit of profits from releasing HBM. Memory prices have increased several times this year. According to Gartner, memory costs account for 35% of new PCs. High memory prices will cause the PC market to shrink by more than 10% by the end of this year.
Secondly, the computing power of AI accelerators is growing faster than the storage capacity of HBM. If the first tripled productivity in two years, the second improved performance less than twice in that period. As a result, AI accelerators are limited by memory bandwidth, limiting their speed. Micron itself is trying to deliver HBM4 faster than the JEDEC standard requires, but this is unlikely to be enough to close the gap. The height of the HBM stack can be easily grown to 16 layers, but beyond this number further expansion may encounter technical difficulties.
Rival SK Hynix said at the Hot Chips 2026 conference that the maximum stack height will be limited to 775 microns before HBM manufacturers move to hybrid splicing technology, but this will only happen as part of HBM5 wafer production. As Micron admits, as memory density increases, thermal conditions become a serious issue. The base crystal, which is the hottest during operation, is located at the bottom of the stack, furthest from the cooling system heat sink, and in contact with the top crystal in the stack. Micron now pays great attention to solving thermodynamic issues when developing HBM. Overheating is becoming one of the most obvious threats to the stability of artificial intelligence computing infrastructure.
Analysts expect that DDR5 single-chip profitability will be higher than HBM3E by the end of this year as the price of first-class memory continues to rise. Manufacturers are already able to make so much money on DDR5 that they will have no incentive to commission additional capacity for its production. As many memory market participants believe, the DRAM shortage will continue next year.
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