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Apple’s future iPhone A20 Pro processor architecture exposed: GPU increased to 7 cores

Olivia Bennett by Olivia Bennett
September 3, 2026
in Games
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Apple’s future iPhone A20 Pro processor architecture exposed: GPU increased to 7 cores
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The first images of the A20 Pro chip reveal key hardware innovations for the upcoming iPhone 18 Pro and iPhone Fold. Here are the details.

iPhone Extreme Edition

Upcoming corporate events in September will be the stage for the debut A20 Pro ProcessorApple’s first 2nm system-on-chip for phones. The first visual analysis of the component’s internal structure confirms Major architectural changesmarked as transition to WMCM packaging technology thereby compromising the solutions used in the past.

This new construction method will allow processors to incorporate composite graphics units Equipped with 7 cores for the first timesignificantly improving the performance of multimedia workloads. A20 Pro will power new flagship smartphone range, models included iPhone 18 Pro, iPhone 18 Pro Max and the company’s first foldable device, l’iPhone Ultra (folded).

La CPU del Chip Apple A20 Pro

As for the main processing parts, CPU configuration will remain unchangedkeep 2 High-performance core with 4 high-efficiency cores. The choice not to increase the total number of modules was made in response to the desire to save energy consumption while ensuring an important improvement in computing speed compared to competitors.

iPhone Ultra’s design and hinge surprise first testers, but not everything is convincing

iPhone Ultra's design and hinge surprise first testers, but not everything is convincing

Cache analysis highlights that the 2 high-performance cores will maintain the L2 value of 16 MB, exactly like the previous generation. Instead, improvements focus on High efficiency modulewhere the second-level cache From 6 terabytes to 8 terabytesproviding greater responsiveness in daily operations.

Big news about Apple A20 Pro chip RAM management

The real architectural breakthrough involves RAM management: WMCM packaging positions memory modules Aligned with processors instead of overlapping. This arrangement allows the bus width to be expanded to 96 bits while maintaining the LPDDR5X standard, which is a bandwidth-increasing measure No need to adopt more expensive LPDDR6 technology.

Source: Wccftech.com
Source: Wccftech.com

At this time, the exact details of the parts related to artificial intelligence and image processors remain unknown, because they are not yet identifiable in the filtered image. However, actual feedback on live consumption and performance will only be verified when the first cognitive tests are released on the sidelines of official presentations.

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