At the Hot Chips 2026 conference, Intel talked about the technical challenges and goals behind the development of Core Series 3 (Wildcat Lake) mobile processors. Essentially, they are a cheaper version of the Core Ultra 3 (Panther Lake) and built on top of it.
Image credit: HardwareLuxx/Intel
According to Intel, the goal of Wildcat Lake is not to develop an entirely new architecture, but to selectively reduce the cost of existing designs without sacrificing features important to mainstream users. The strategy is based on three pillars: MCP packaging technology (not Foveros), “optimization” of modules and platforms, and innovation focused on one technology area – the use of the UCIe inter-chip bus.
Core Ultra 3 series chips use Foveros technology to connect multiple small chips through a passive substrate (silicon interposer). However, this approach is too expensive for mainstream market processors, including Wildcat Lake chips, and the cost advantage is crucial. As a result, Core Series 3 eliminates the base die entirely and adopts an organic multi-chip design (MCP). This not only reduces wafer complexity, but also reduces wafer assembly costs and yield losses associated with Foveros multi-layer designs.
However, the transition to MCP is not without its drawbacks. Without a backplane, the processor chip would be able to process far fewer signals. Additionally, power management must be re-optimized to fully realize the benefits of simpler packaging. One of the technical requirements is that the wafer used must be monolithic or designed specifically for MCP/organic packaging.
The transition to MCP also affects the physical characteristics of Wildcat Lake processors. If the Foveros package size of the Core Ultra Series 3 chip is 50 × 25 × 1.5 mm, the organic MCP package size of the Core Series 3 processor will be reduced to 35 × 25 × 1.23 mm. The smaller package saves board space, requires fewer I/O interfaces, allows variable power supplies, and there are no more dead contacts in the package.
In terms of computing chips, Intel 18A process technology is still used – it provides higher CPU core performance and efficiency, and has been used in the Core Ultra 3 series. However, for the I/O interface modules (Thunderbolt, USB 2.0, PCIe), the TSMC N6 process technology that is also familiar in the Core Ultra 3 series is used. UCIe die interconnect technology is available for all technology flows under consideration (Intel 3, Intel 18A, TSMC N6) and is therefore the obvious choice for connecting two crystals to form Wildcat Lake.
When developing Wildcat Lake, it was particularly important to maintain the different technology flows used in Core Ultra 3 processors and the use of small die components. This saves processor verification, planning and design costs without changing the user experience, for example in terms of single-thread CPU performance or USB 2.0 support.
Since abandoning the Foveros base crystal required the use of new die-to-die technologies, the UCIe (Universal Chiplet Interconnect Express) bus was chosen for these purposes. However, without the base die, the pad spacing increases significantly – from 36 µm for Foveros to 110 µm for UCIe. This has many consequences: higher data rates (GT/s) are required to compensate for lower pin density, and the area occupied by the I/O interface block and controller increases. Overall, the inter-die area of Core Series 3 processors is approximately 70% larger than that of Core Ultra Series 3 processors. Intel believes this trade-off is reasonable given the MCP packaging cost savings.
In order not to increase the occupied area, the throughput of the I/O block is optimized specifically for massive segments. The target is a PCIe 4.0 SSD connection with data transfer speeds of approximately 12 Gbps (16 read/write lanes, 8 GT/s). Display connectivity has also been optimized – from UHBR20 to 4K60 (adapted to HDMI/eDP levels in Raptor Lake-U processors) with speeds of 16 W and 8 GT/s. In addition, the number of sideband signals (Sideband Signal Count Diet) has also been reduced.
Protocol issues. UCIe packs the data, which introduces some latency, but the slower sideband signals are not initially affected. Because the UCIe bus is directly integrated into boot, debug, security, and display protocols, synchronization between data and control signals was one of the most challenging verification tasks of the entire project. As a precautionary measure, circuit breakers and survivability options have been implemented to ensure reliable UCIe startup.
Energy management. Packing inherently increases power consumption since frequency should ideally be maintained continuously to avoid wasted latency. Display-related traffic is particularly important because it is transmitted over UCIe even in standby mode, especially without panel self-refresh (PSR). This brings up the biggest problem of energy consumption. As a countermeasure, multiple link states were introduced and QoS prioritization was implemented for mapping related traffic.
Signal integrity. At high frequencies, UCIe faces challenges related to tight voltage tolerances and bit error rates (BER). Initially, Intel considered two I/O voltage options: using a dedicated LDO regulator (a cleaner but more expensive option) or the existing VCCAON power rail. As a result, LDO stabilizers were deprecated. Data transfer rates are limited to a maximum of 8 Gbps, and there are no retry or forward error correction mechanisms. Instead, there are fallback options to reduce frequency—an intentionally lower-risk, but more resource-intensive approach.
Compared to Core Ultra Series 3, Wildcat Lake’s overall processing power is significantly reduced:
- The number of built-in Xe graphics cores has been reduced from four to two, and the XMX matrix engine (to accelerate artificial intelligence) is retained, but ray tracing has been deleted;
- The number of NPU cores is reduced from 3 to 1, and TOPS performance drops from 53 to 17;
- The number of computing P cores is reduced from 4 to 2, and the last-level cache capacity is reduced from 12MB to 6MB, but the performance in single-thread mode remains unchanged;
- The IPU (Image Processing Unit) has been completely removed. Instead, the camera connects via USB2 ISP;
- Removed Pro-Media functionality;
- The memory interface is reduced from 128-bit to 64-bit LP5, and the system cache is reduced from 4MB to 2MB;
- The number of display channels is reduced from 4 to 3, and the maximum throughput is reduced from UHBR20 to 4K60.
Overall, these changes resulted in a 38% reduction in the area of the graphics and computational crystals. I/O capabilities are also reduced. The number of Thunderbolt/USB4 ports has been reduced from 3 (4 eDP multiplexing) to 2, PCIe is completely unified to 6 Gen4 (instead of the previous 4 Gen5 + 8 Gen4), and the number of USB ports remains unchanged – 2 USB3.2 and 8 USB2. The Physical Camera PHY Interface (CSI) has been completely removed. The number of supported audio channels has been reduced from 4 to 2, the number of digital signal processors has been reduced from 5 to 3 (but run at a higher frequency), and the associated memory amount has been reduced from 4.6 MB to 3.0 MB. Overall, die area is reduced by 15% due to I/O block optimization.
Based on a reference system with a Core 7 150U processor (Raptor Lake-U Refresh), additional savings are achieved at the platform level: transitioning from 128-bit DRAM to 64-bit DRAM reduces the number of layers on the printed circuit board from eight to six and adjusts the location of the DRAM and SODIMM connectors. For power delivery technology, an additional LP Atom voltage rail is added to extend battery life while increasing maximum full load current draw and load capacity. The Wi-Fi 7 module is directly integrated, as is the PD controller (built into the USB retimer).
The Core Series 3 processor family is an example of how an existing high-performance architecture (Panther Lake) can be redesigned for mainstream market segments. Significant cost reductions can be achieved due to the transition from Foveros technology to organic MCP packaging, optimization of computing units, graphics and neural processor units, I/O units, and platform-level savings (simplified DRAM interface, fewer PCB layers, built-in Wi-Fi and PD controllers). At the same time, critical user functionality is preserved by reusing technical standards, dividing the crystal into blocks, and maintaining single-thread performance. The only fundamental new technology component is the UCIe interconnect system, which compensates for the elimination of the Foveros base chip, but requires a significant increase in interconnect volume (+70%) and presents certain difficulties in timing, power consumption and signal integrity.
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